Processor Microarchitecture

Description

This course unit aims to reinforce and extend digital hardware development skills which are introduced in the first year. It aims to give students a view of the role of the digital designer, taking an idea and implementing it in silicon. The course unit looks at different architectures and computing paradigms, finishing with a discussion of what technologies may, in the future, replace silicon as the building block of the processor. The syllabus is given below with the sections associated with each concept. First half 1. Introduction Overview, introduction to the lab, approaches to design and the management of complexity 2. Introducing Stump Designing complex systems, RISC v CISC, Stump specification and addressing schemes, Stump ISA 3. Verilog & Testing Verilog recap and new features - tasks, functions and structural Verilog. Verification, validation and testing - the testbench. 4. Sequential systems design The processor as a sequential system, datapath and control, register transfer level (RTL) design, Mealy and Moore finite state machines. 5. Designing and Implementing Processors Implementation of processors from the ISA, architectural design, RTL design, Verilog implementation. 6. Introduction to CMOS Basic electronics, logic gates in CMOS and design considerations. Second half 7. Specialised Processing Architectures Examining DSPs, floating-point (and other) coprocessors, SIMD and vector extensions as well as VLIW. 8. Microarchitectural Structures Basic building blocks, including register files, FIFOs, RAMs, CAMs, arithmetic circuits (adders and multipliers) and shifters. 9. FPGAs FPGA mode of operation and its spatial programming model as well as application examples. 10. Technology & Hardware Design Examples Standard Cell design methodology, PLA, Multiplexer, look-up table technology, investigating circuits and design factors. 11. Computer Aided Design (CAD) Tools Logic synthesis, constraints, Place & Route, DRCs. 12. Verification and Testing Analogue and digital simulation, regression testing, production test and yield built-in self-test (BIST). 13. Timing and Clocking System performance, setup and hold times, jitter, clock skew, clock distribution networks, propagation delay, signal integrity, static timing analysis (STA), clock domains, synchronisation and meta-stability. 14. Future Limits of Moores' law, understanding the importance of energy efficiency, new manufacturing techniques, memristor-based computing, exotic technologies (Quantum dots, Graphene, Spintronics, etc.). Assessment Information: Method Weight Written exam 50% Practical skills assessment 50%